1. Field of the Invention
The present invention relates to the field of plastic encapsulation of semiconductor devices and more specifically to the encapsulation of multi-lead integrated circuits within a plastic carrier.
2. Prior Art
During the early development of encapsulating integrated circuits, the integrated circuits were typically packaged in a metal or a ceramic shell. Although ceramic encapsulation is effective, ceramic insulation is costly and reflect a sizable percentage of the total cost of manufacturing an integrated circuit chip. More recently, plastic encapsulation techniques have been devised which substantially lower the cost of packaging an integrated circuit device.
In a typical plastic packaging technique, an integrated circuit, usually in a form of a die, is placed proximate to a leadframe. The chip or the die is then wired such that various terminals of the integrated circuit are physically connected to the leads of the leadframe by wires. Next, the integrated circuit chip is bonded and potted such that the chip is encapsulated within the plastic package and only the leads extend externally of the package.
The conventional single-layer molded plastic package using metal leads as known in the prior art typically require one-to-one connection of the various integrated circuit terminals on the die to the leads. The number and position of power and ground leads of the package were directly dependent on the number and position of the power and ground bond pads on the die. Although multiple connections could be made to the various power and ground leads from the die pads, such practice places additional constraint in positioning the various pads. Also, in certain high current applications, additional pads and leads are needed to shunt the additional current. Increase in the number of power and ground pads on the die which result in the increase in the number of leads ultimately cause high electrical inductance and low capacitance to exist between the power and ground pads, such that these properties cause low speed response of the integrated circuit. Further, increase in the number of bond pads on a single layer package dictates an increase in the package lead count resulting in an increase in the size of the package and inhibiting any attempt at package shrink.
Also due to the fact that a single layer molded plastic package is basically flat and causes all I/O (input/output) to ground lead current loops to lie in one plane, cross talk on high lead count packages is appreciably significant to cause communication degradation.
Where prior art single-layer molded plastic packages are quite adequate for various low lead count or low speed integrated cirucuits, a high lead count, high speed integrated circuit implemented in a compact plastic package is difficult to achieve using prior art techniques. It is appreciated then that what is needed is a plastic package for encapsulating a high speed, high lead count integrated circuit, such as a 32-bit microprocessor chip, in a compact system.